1. Field of the Invention
The present invention is related to the field of bit stream based systems and more particularly to an automated system for host register interface testing.
2. Description of the Relevant Art
Comprehensive verification of host register interfaces provided by programmable chips is a difficult task that is consuming an increasing amount of resources with the advent of increasingly complex system-on-a-chip style application specific integrated circuits (ASIC's). These ASICs may include a large number of programmable operation modes available through a set of host registers. Traditionally, a set of separate tests has been crafted to verify each feature or operating mode of a device independently. Typically, a test template source code is used as a starting point. The various tests are then generated by modifying appropriate parameters in the template source code. Unfortunately, this traditional approach requires a time consuming recompilation of source code each time a new test is to be run. This results in a large number of test programs that have to be executed sequentially to achieve adequate verification coverage of the host register interface. In addition, the process must be repeated for each new revision of a device to ensure compatibility with previous versions. Because this traditional approach to verification is a time consuming process, it would be desirable to implement a system that generated the required test cases automatically.